1. Field of the Invention
The present invention relates to a power transistor device which has a high secondary breakdown strength, and also to a substrate arrangement for such as power transistor device, and a method for making the same.
2. Description of the Prior Art
When a transistor is used with its emitter grounded, a secondary breakdown will take place if a reverse direction voltage between the collector and emitter increases. The secondary breakdown is mainly due to the thermal unstableness in the lateral direction which causes electric current concentration locally in the unstable area, resulting in the breakage of the transistor. One method to increase the stable operating range (ASO) of the power transistor is to divide the emitter portion into a number of sections to equally divide the emitter current, and connect an emitter stabilizing resistor to each divided emitter section. If the emitter current through a particular section should abnormally increase, the voltage drop across the emitter stabilizing resistor produces a negative feed back current, thereby preventing the local concentration of the emitter current. Such a method and arrangement is disclosed, for example, in Japanese Patent Publication No. 56-13383 issued Mar. 27, 1981.
A typical example of a prior art power transistor is shown in FIG. 8 in which reference number 1 is an N.sup.+ type collector region, 2 is an opening for connecting the collector region 2, 3 is a P type base region, 4 is an opening for connecting the base, 5 is an N.sup.+ type emitter region, 6 is an emitter connecting region, 7 is an opening for connecting the emitter, 8 is a resistor region for providing the emitter stabilizing resistor 9 which usually has about 1 to several ohms.
However, according to the arrangement shown in FIG. 8, a distance between two neighboring emitter contact regions 6 is rather long, and thus there will be produced non-contributing area on the surface of the base region 3. Thus, when the arrangement shown in FIG. 8 is employed, it is difficult to reduce the size thereof.
Furthermore, if the resistance of the emitter stabilizing resistor is made large, the secondary breakdown can be avoided, but such a transistor will result in a low efficiency, i.e., narrowing the dynamic range of the transistor. On the other hand, if the resistance of the emitter stabilizing resistor is made small, the operating range of the negative feedback effected by the negative temperature coefficient characteristics of the resistor region 8 will be narrowed.
In light of the above, in order to optimize the arrangement of the power transistor device, the resistance of the emitter stabilizing resistors should be made as small as possible, and as uniform as possible.
However, according to the prior art arrangement shown in FIG. 4, since the resistor region 8, emitter region 5 and the emitter contact region 6 are provided in the same diffusion layer, the change of the width W of the resistor region 8 will eventually change the length L thereof. Thus, the emitter stabilizing resistor 9 varies greatly, thus making it difficult to reduce the resistance of such a resistor.